1. Field of the Invention
The embodiments discussed herein relate to a switching power supply control circuit and a switching power supply and particularly to a switching power supply control circuit and a switching power supply that optimize a noise reduction effect by giving jitter (frequency diffusion) to a switching frequency.
2. Background of the Related Art
Switching power supplies convert a commercial alternating-current (AC) voltage into any direct-current (DC) voltage and output the converted DC voltage. Switching power supplies need a small number of components and are applicable to a wide input voltage range. For example, flyback switching power supplies in which the output voltage is insulated from a commercial power supply are known.
FIG. 22 is a circuit diagram illustrating an example of a typical configuration of a flyback switching power supply 100.
As illustrated in FIG. 22, this flyback switching power supply 100 includes a control integrated circuit (IC) 8, which is a control circuit for controlling pulse width modulation (PWM), a transformer T, a diode 19, a capacitor 20, and a switching element. In FIG. 22, a metal-oxide-semiconductor field-effect transistor (MOSFET) 17 is used as the switching element.
A commercial AC power supply 1 is supplied to a diode bridge 4 via a common mode choke coil 2 and an X capacitor 3 forming an input noise filter, and the diode bridge 4 performs full-wave rectification on the AC power supply 1.
A capacitor 5 is arranged between the diode bridge 4 and the ground. The capacitor 5 holds an input voltage so that energy is stably supplied to the output side. In addition, the capacitor 5 absorbs the switching noise that occurs when the MOSFET 17 performs its switching operation. In addition, a diode 6 performs a half-wave rectification on the AC power supply 1 and supplies the AC power supply 1 to a VH terminal of the control IC 8 via a current-limiting resistor 7. In this way, the power supply voltage of the control IC 8 at the time of startup is ensured. This current-limiting resistor 7 limits the input current supplied to the VH terminal.
The control IC 8 includes a LAT terminal connected to a thermistor 9 that provides overheat latch protection for the control IC 8. In addition, the control IC 8 includes a CS terminal to which a voltage across a sense resistor 12 is applied via a capacitor 10 and a resistor 11 forming a noise filter.
In addition, the control IC 8 includes a VCC terminal connected to one end of a capacitor 13 and to an auxiliary winding 15 of the transformer T via a diode 14. The capacitor 13 holds the power supply voltage that is supplied to the control IC 8 when a PWM control operation is performed. The diode 14 supplies a voltage to the VCC terminal from the auxiliary winding 15 after startup.
The transformer T includes a primary winding 16, one end of which is connected to the capacitor 5 and the other end of which is connected to the drain terminal of the MOSFET 17. The source terminal of the MOSFET 17 is connected to the ground via the sense resistor 12, and this sense resistor 12 detects a drain current Ids that flows through the MOSFET 17. Namely, the sense resistor 12 converts the on-current of the MOSFET 17 into a voltage signal that is proportional to the magnitude of the on-current, and this voltage signal (current detection signal) is inputted to the CS terminal of the control IC 8 via the noise filter.
The transformer T includes a secondary winding 18 connected to one end of the diode 19 and to the ground via the capacitor 20. The voltage across the capacitor 20 is the output voltage applied to a load 25, and information about this voltage is transmitted from the secondary side to the primary side by a photocoupler 21. The photocoupler 21 is connected in series with a shunt regulator 22, which is connected to the connection point of resistors 23 and 24 that divide the output voltage. This shunt regulator 22 compares a value obtained by dividing the output voltage with an internal reference voltage. In addition, the shunt regulator 22 converts information about the error between the secondary-side output voltage and the reference voltage into a current signal. When this current signal flows through a light emitting diode (LED) included in the photocoupler 21, the current signal is converted into a light signal, which is transmitted to a phototransistor included in the photocoupler 21. In this way, information about the secondary-side output voltage, namely, load information, is transmitted to the primary side.
The switching power supply 100 including the control IC 8 for controlling PWM controls the switching operation of the MOSFET 17 and causes the transformer T to convert the voltage obtained by rectifying the AC input voltage into a predetermined DC voltage.
The control IC 8 configured by an IC circuit includes an FB terminal, and the load information outputted to the load 25 arranged on the secondary side of the transformer T is fed back to and detected by the FB terminal via the shunt regulator 22 and the photocoupler 21 as described above.
In addition, the drain current Ids of the MOSFET 17 is converted by the sense resistor 12 into a voltage, and this voltage is detected by the CS terminal of the control IC 8. The control IC 8 determines an output signal from its OUT terminal by directly or indirectly comparing the voltages at the respective FB and CS terminals. By varying the on-width of the MOSFET 17 based on this output signal, PWM control on the switching power supply is performed. In this way, the power supplied to the load 25 on the secondary side is adjusted.
FIG. 23 is a block diagram illustrating an example of a circuit configuration of the control IC 8.
In the control IC 8, a start-up circuit 31 supplies a current from the VH terminal to the VCC terminal at the time of startup. When the AC power supply 1 is applied, a current flows from the VH terminal to the VCC terminal via the start-up circuit 31 in the control IC 8. As a result, the external capacitor 13 connected to the VCC terminal is charged, and the voltage value of the capacitor 13 is increased.
An under voltage lock out (UVLO) circuit 32 is connected to the VCC terminal and a reference power supply V1. When the voltage value at the VCC terminal (VCC voltage) reaches the reference power supply V1 or more, this UVLO circuit 32 outputs a low (L) level UVLO signal, and an internal power supply circuit 33 is started. Consequently, power is supplied to various circuits in the control IC 8. In contrast, when the VCC voltage is low, the UVLO circuit 32 outputs a high (H) level UVLO signal to stop the operation of the control IC 8.
An oscillator (OSC) 34 is connected to the FB terminal and includes a frequency modulation function, with which the oscillator 34 performs frequency diffusion to reduce the electromagnetic interference (EMI) noise that occurs when the MOSFET 17 performs its switching operation. This oscillator 34 determines the operating frequency of the MOSFET 17 of the control IC 8, includes, in addition to the above frequency modulation function, a frequency varying function to decrease the oscillation frequency when the load is light, and outputs an oscillation signal (maximum duty signal) Dmax.
This oscillation signal Dmax is a signal that is brought in an H level for a long time and in an L level only for a short time per cycle. The cycle of the oscillation signal Dmax is a switching cycle of the switching power supply. The ratio between the period of the cycle and the H-level time thereof represents the maximum duty of the switching power supply. In addition, a slope compensation circuit 35 is connected to the CS terminal and includes a function of preventing subharmonic oscillation, which will be described below.
A FB comparator 36 has input terminals connected to the FB terminal and a reference power supply V2. When the voltage at the FB terminal (FB voltage) falls below the reference power supply V2, the FB comparator 36 determines that the load power is small, outputs a clear signal CLR to a downstream one-shot circuit 37, and stops the switching operation. In contrast, when the FB voltage exceeds the reference power supply V2, the FB comparator 36 starts the switching operation. In this way, the FB comparator 36 realizes a burst operation in which the switching operation is temporarily stopped when the load is light.
When the oscillation signal Dmax outputted from the oscillator 34 rises, the one-shot circuit 37 generates and outputs a set pulse to a downstream RS flip flop 38. This set pulse also serves as a blanking signal that prevents the MOSFET 17 from being erroneously turned off by the noise that occurs at the CS terminal when the MOSFET 17 turns on. The one-shot circuit 37 does not output the set pulse to the RS flip flop 38 while receiving an H-level clear signal CLR.
The RS flip flop 38 generates a PWM signal, along with an OR gate 39 and an AND gate 40. Namely, the OR gate 39 uses the output signal from the one-shot circuit 37 and the output signal from the RS flip flop 38 and generates an OR signal of the two output signals.
While the output signal from this OR gate 39 is basically used as the PWM signal, the AND gate 40 determines the maximum duty of the PWM signal on the basis of the oscillation signal Dmax from the oscillator 34.
The UVLO signal outputted from the UVLO circuit 32 is supplied to a drive circuit (OUTPUT) 42 via an OR gate 41 and controls whether to allow the drive circuit 42 to operate. The drive circuit 42 outputs a switch signal Sout via the OUT terminal, to control the switching of the MOSFET 17. Namely, when the VCC voltage is low and the UVLO circuit 32 outputs a high-level UVLO signal, the output from the drive circuit 42 is turned off (the drive circuit 42 outputs a signal that turns off the MOSFET 17). In contrast, when the VCC voltage is high, the UVLO circuit 32 outputs a low-level UVLO signal, and a latch circuit 49 outputs a low-level output signal, the drive circuit 42 controls the switching of the MOSFET 17 in accordance with the output signal from the AND gate 40.
A level shift circuit 43 has a function of shifting the level of the FB voltage so that the voltage falls within the input voltage range of a CS comparator 44. The shifted output signal from the level shift circuit 43 is supplied to the inverting input terminal (−) of the CS comparator 44. The non-inverting input terminal (+) of the CS comparator 44 is supplied with an output signal from the slope compensation circuit 35. An internal power supply voltage is supplied to the FB terminal via a resistor R0, which serves as a load resistor (pull-up resistor) of the phototransistor included in the photocoupler 21. In this way, the voltage from the internal power supply circuit 33 drops at the resistor R0, and the magnitude of an error signal, which represents amplification of the difference between the voltage applied to the load 25 connected to the switching power supply 100 and the reference voltage, is detected. A larger error signal (a larger voltage at the FB terminal) indicates heavier load.
The CS comparator 44 compares the voltage at the CS terminal (CS voltage) on which slope compensation has been performed to prevent subharmonic oscillation with the FB voltage whose level has been shifted and determines when the MOSFET 17 turns off.
In addition, an OCP comparator 45 is connected to the CS terminal of the control IC 8. The OCP comparator 45 determines the overcurrent detection level of the MOSFET 17. The OCP comparator 45 has a non-inverting input terminal (+) connected to the CS terminal and an inverting input terminal (−) connected to a reference power supply V3.
An off-signal from the CS comparator 44 is supplied to a reset terminal of the RS flip flop 38 via an OR gate 46. In addition, after a delay time control circuit 50 adjusts delay time, an off-signal from the OCP comparator 45 is supplied to the reset terminal of the RS flip flop 38 via the OR gate 46.
A current is supplied from a current source 47 to the thermistor 9 via the LAT terminal. A LAT comparator 48 is connected to the LAT terminal and a reference power supply V4. When the LAT comparator 48 detects that the voltage at the LAT terminal (namely, the voltage across the thermistor 9) reaches the reference power supply V4 or lower, the LAT comparator 48 determines that the control IC 8 is overheated and outputs a set signal to the latch circuit 49.
When receiving the set signal from the LAT comparator 48, the latch circuit 49 outputs an H-level latch signal Latch to the OR gate 41 and an OR gate 51. As a result, the drive circuit 42 is turned off, and the start-up circuit 31 is turned on. In addition, the latch circuit 49 has a reset terminal provided with the UVLO signal from the UVLO circuit 32. When the potential at the VCC terminal is decreased, the latch state is canceled.
When the internal power supply circuit 33 is started and power is supplied to internal circuits, a voltage is applied to the phototransistor included in the photocoupler 21 via the resistor R0 and the FB terminal, and the FB voltage is increased.
When the voltage signal at the FB terminal reaches a fixed voltage value or more, the oscillation signal Dmax is outputted from the oscillator 34. When the oscillation signal Dmax rises, the one-shot circuit 37 outputs a set pulse to the RS flip flop 38.
This set pulse and the output signal from the RS flip flop 38 are inputted to the OR gate 39. Next, the OR gate 39 outputs a PWM signal to the AND gate 40 and the drive circuit 42, and the drive circuit 42 outputs the switch signal Sout to the gate terminal of the MOSFET 17 via the OUT terminal, to drive the MOSFET 17.
In this way, the MOSFET 17 is turned on at a rising edge of the oscillation signal Dmax. As described above, the OR gate 39 generates an OR signal of the output signal from the RS flip flop 38 and the set pulse from the one-shot circuit 37. This is to prevent the RS flip flop 38 from being reset by the noise that occurs at the CS terminal when the MOSFET 17 is turned on and the MOSFET 17 from being turned off immediately after being turned on.
When the MOSFET 17 turns on, since the drain current Ids flows through the sense resistor 12, the voltage at the CS terminal of the control IC 8 increases. Next, the slope compensation circuit 35 of the control IC 8 performs slope compensation on the CS voltage. When this voltage reaches the level of the FB voltage shifted by the level shift circuit 43, the CS comparator 44 outputs a reset signal to the RS flip flop 38 via the OR gate 46.
When the RS flip flop 38 is reset, the OR gate 39 outputs an L-level signal (in a normal operation, the set pulse from the one-shot circuit 37 represents an L level at this point). Consequently, the AND gate 40 outputs an L-level signal, and the MOSFET 17 is turned off by the switch signal Sout.
In addition, even when the load 25 connected to the switching power supply is very heavy and the voltage value fed back to the FB terminal of the control IC 8 falls out of the control range (on the high voltage side), the MOSFET 17 is turned off. Namely, when the OCP comparator 45 compares the CS voltage with the reference power supply V3, if the CS voltage is equal to or more than the reference power supply V3, the MOSFET 17 is turned off.
Before the CS comparator 44 compares the FB voltage whose level has been shifted with the CS voltage, the slope compensation circuit 35 performs slope compensation on the CS voltage. In this slope compensation, the slope compensation circuit 35 adds a slope compensation voltage proportional to the on-width of the MOSFET 17.
Generally, as long as the MOSFET 17 operates in a steady state, a current having a constant magnitude flows through the MOSFET 17 at the beginning of each switching cycle. However, when the duty (duty cycle=on-width/switching cycle) of the MOSFET 17 is excessively increased, the magnitude of the current does not remain constant. Namely, per switching cycle, the state of the current flowing through the MOSFET 17 fluctuates. If this occurs, the current flowing through the MOSFET 17 behaves as a signal in which a low frequency signal is superimposed on the switching frequency signal.
Such an oscillation at a low frequency is known as subharmonic oscillation, which is caused under a certain condition. Occurrence of the subharmonic oscillation can be prevented by preventing this condition from being met, more specifically, by performing slope compensation in which a monotonically increasing signal is superimposed on the CS voltage.
In the switching power supply 100, the oscillator 34 of the control IC 8 generates the oscillation signal Dmax for causing the MOSFET 17 to perform its switching operation. Typically, a frequency between 65 kHz and 25 kHz is used. Namely, the switching frequency is fixed at 65 kHz when the load 25 is heavy, and the switching frequency is changed from 65 kHz to 25 kHz as the load 25 becomes lighter. When the switching frequency is decreased down to 25 kHz, the switching frequency is fixed at 25 kHz. Namely, the switching frequency is prevented from decreasing to the audible frequency at which the transformer T causes noise. In this way, since the operating frequency is decreased as the load becomes lighter, the efficiency of the switching power supply 100 is improved.
For example, when the switching frequency is fixed at 65 kHz, high-order harmonics having a fundamental wave of 65 kHz are simultaneously generated, and these high-order harmonics are released to the outside of the switching power supply 100 as radiated EMI and conducted EMI. Since such EMI noise negatively affects operations of other electronic devices, a limit that prohibits more than a certain amount of EMI noise is defined. Hereinafter, conducted EMI noise that is transmitted through cables or substrate wirings will be described.
In the field of power electronics including the switching power supply 100, jitter (frequency diffusion) is used to reduce conducted EMI noise (for example, see International Publication No. 2006/019196, Japanese Laid-open Patent Publication No. 2003-150660, and YAMADA Tomonori, IMAZATO Masaharu, and YOSHINAGA Takashi, “Estimation of the EMI Reduction by Spread Spectrum Clock,” The Institute of Electronics, Information and Communication Engineers (IEICE) Technical Report, Engineering Sciences Society IEICE, Dec. 21, 2001, vol. 101, no. 530, pp. 37-42 (hereinafter, YAMADA).
FIG. 24 illustrates the difference in noise energy between when jitter is used and when jitter is not used, and FIG. 25 illustrates a modulation frequency. In FIG. 24, the horizontal axis represents the switching frequency, and the vertical axis represents the noise energy. The right graph in FIG. 24 illustrates center diffusion in which an operating frequency fc corresponding to when jitter is not used is diffused within ±Δ f/2.
As illustrated on the left graph in FIG. 24, when jitter is not used, the noise energy is significantly high and reaches its peak at the operating frequency fc. In contrast, if the operating frequency fc is diffused within ±Δ f/2, the noise energy is also diffused, and the average value and the peak values of the noise energies are reduced. Namely, even when jitter is not used and the peak of the noise energy is above the limit, if jitter is used, the peaks equal to or less than the limit are obtained. While the frequency diffusion is performed by modulating the operating frequency fc with a modulation frequency fm, the waveform of the modulation frequency fm (hereinafter, the waveform that indicates the time change of the operating frequency fc modulated by the modulation frequency fm or a signal that corresponds to the operating frequency fc) is formed by a multi-bit digital signal. When the output from a counter is directly applied as the multi-bit digital signal, the waveform of the modulation frequency fm changes in a stepwise manner.
FIG. 26 illustrates a noise level reduction effect obtained when the switching frequency is diffused. In FIG. 26, the horizontal axis represents the diffusion width and the vertical axis represents the attenuation amount. More specifically, FIG. 26 illustrates the noise attenuation amount when the operating frequency fc of the fundamental wave is 65 kHz and the resolution bandwidth RBW, which is the measurement frequency width, is 9 kHz.
As illustrated in FIG. 26, a wider diffusion width achieves a larger attenuation amount S, namely, a larger noise level reduction effect.
Since the current standard for conducted EMI defines that the frequency range in which the EMI noise is measured is from 150 kHz to 30 MHz, it is only enough to examine the attenuation effects about harmonics of 150 kHz or more. As illustrated from FIG. 26, 20 kHz or more needs to be ensured as the diffusion width (Δf), to obtain an attenuation amount of 3 dB or more. Hereinafter, two basic switching operations, performed when the operating frequency fc is 65 kHz and 25 kHz, respectively, will be described, assuming that the diffusion width is ±7% of the operating frequency fc. Namely, the switching power supply 100 operates at 65 kHz±4.55 kHz when the load is heavy and operates at 25 kHz±1.75 kHz when the load is light.
When the operating frequency fc is 65 kHz±4.55 kHz, a harmonic of 150 kHz or more does not appear until the order n reaches 3. The frequency of this third harmonic is 3×(65 kHz±4.55 kHz)=195 kHz±13.65 kHz, and the diffusion width is 27.3 kHz. Regarding a harmonic, the higher the order is, the smaller the energy will be. Thus, if the third harmonic falls below the EMI limit, the attenuation amounts of the fourth harmonic and subsequent harmonics do not need to be considered, except phenomena such as ringing in a discontinuous current mode (DCM).
When the operating frequency fc is 25 kHz±1.75 kHz, a harmonic of 150 kHz or more does not appear until the order n reaches 6. The frequency of this sixth harmonic is 6×(25 kHz±1.75 kHz)=150 kHz±10.5 kHz, and the diffusion width is 21 kHz.
Thus, by setting the diffusion width to ±7% with respect to each of the operating frequencies fc (65 kHz and 25 kHz) of the switching operation, the diffusion width of 20 kHz or more is ensured, and an attenuation amount of 3 dB or more is obtained in the frequency range in which the EMI noise is measured.
FIG. 27 is a circuit diagram illustrating a configuration example of an oscillator having a jitter control circuit 70 that performs frequency diffusion. FIG. 28 is a circuit diagram illustrating a configuration example of the jitter control circuit 70.
As illustrated in FIG. 27, the oscillator 34 includes a buffer amplifier 61 that detects a feedback voltage FB and an amplifier 62 that controls the current that flows through a transistor (n-channel MOSFET) N1 on the basis of the output from the buffer amplifier 61. The transistor N1 is connected to a current mirror circuit formed by transistors (p-channel MOSFETs) P1 and P2, and the current that flows through the transistor N1 is a first input current of the current mirror circuit. In addition, a current source is connected between the drain terminal of the transistor P1 and the ground, and the current from the current source is a second input current of the current mirror circuit. The current outputted from the current mirror circuit is supplied to a transistor N2 connected to the drain terminal of the transistor P2, which is an output terminal of the current mirror circuit, and the supplied current is used to control the current that flows through a transistor N5. In addition, the current outputted from the current mirror circuit is used to control the current that flows through a transistor P4 via transistors N3 and P3.
The transistors P4 and N5 are connected in series with each other via transistor P5 and N4 that are complementarily turned on and off. The connection point between the transistors P5 and N4 is connected to a capacitor C. The transistor P5 charges the capacitor C with the current that flows through the transistor P4 when performing an on-operation. The transistor N4 discharges the capacitor C with the current that flows through the transistor N5 when performing an on-operation. The transistors N2, N3, and N5 form a second current mirror circuit, and the transistors P3 and P4 form a third current mirror circuit.
A hysteresis comparator 63 compares the charging or discharging voltage of the capacitor C with a predetermined reference voltage Vref. The inverter 64 inverts the output from the hysteresis comparator 63 and generates the oscillation signal Dmax for turning on or off the MOSFET 17. Since the hysteresis comparator 63 has hysteresis characteristics, the reference voltage Vref compared with the charging or discharging voltage of the capacitor C is formed by two reference voltages of a high-side reference voltage VrefH and a low-side reference voltage VrefL in practice. In addition, simultaneously, the output from the hysteresis comparator 63 is used as a control signal for complementarily turning on and off the transistors P5 and N4 and as a clock signal that defines the operation of the jitter control circuit 70.
As illustrated in FIG. 28, the jitter control circuit 70 includes a plurality of (four) transistors P11 to P14 that forms a current mirror circuit with the transistor P1 in parallel to each other. These transistors P11 to P14 are connected in series with transistors P15 to P18, respectively. The transistors P15 to P18 are turned on and off in response to outputs Q0 to Q3 from a frequency divider and counter 71, selectively obtain currents flowing through the respective transistors P11 to P14, and add the selected currents to a drain current that flows through the transistor N2.
For example, the currents that flow through the transistors P11 to P14 are set to I1, I2 (=2·I1), I3 (=2·I2=4·I1), I4 (=2·I3=4·I2=8·I1), respectively. The ratio of these currents is set by changing the gate width/gate length of each of the transistors P11 to P14 that form a current mirror circuit with the transistor P1.
The frequency divider and counter 71 divides the frequency outputted from the hysteresis comparator 63 and performs a counting operation. The frequency divider and counter 71 determines the counted value and sequentially changes the outputs Q0 to Q3 within [0000]-[1111], for example. In this way, the transistors P15 to P18 are selectively turned on and off. Accordingly, the currents that flow through the respective transistors P11 to P14 are selectively outputted.
As a result, an output current b from the jitter control circuit 70 changes in a stepwise manner. In FIG. 28, since the output from the frequency divider and counter 71 is represented by 4 bits, the output current b changes in 16 levels and is added to the transistor N2. Next, the current with which the capacitor C is charged is changed in a stepwise manner, and a periodical change is given to the time needed to charge the capacitor C up to the reference voltage Vref. Consequently, the frequency of the pulse signal outputted via the hysteresis comparator 63 is provided with periodical jitter having a certain width. This control on the oscillation frequency is jitter control on the switching frequency for driving the MOSFET 17. By performing this jitter control, the frequency of the EMI noise that occurs when the MOSFET 17 performs switching is diffused, and the EMI noise is accordingly reduced.
According to the current standard for the conducted EMI, the measurement frequency range is over 150 kHz. However, in order to prevent conducted EMI noise from occurring in a lower frequency range, extending the measurement frequency range in which the EMI noise is measured to a frequency less than 150 kHz is under consideration. If the measurement frequency range is extended, the operating frequency of the switching operation, namely, the frequency of the fundamental wave (for example, 65 kHz) having the largest noise energy falls within the measurement frequency range, and measures against the noise need to be taken for the fundamental wave of the switching frequency. An EMI filter may be used to suppress this noise. However, since the frequency is low, constants of an inductor and a capacitor are increased. Accordingly, since the sizes of components are also increased, the size of the switching power supply is increased. As a result, the cost could be increased.